Interrupt Clear register
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| FUFIC | FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt. |
| LNBUIC | LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt. |
| VCOMPIC | Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt. |
| BERIC | AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |